1. Field of the Invention
The present invention relates in general to column redundancy devices for repairing failure memory cells in semiconductor memories, and more particularly to a column redundancy device for a semiconductor memory which is capable of preventing a reduction in a repairing efficiency of failure memory cells although a refresh speed of the semiconductor memory is increased.
2. Description of the Prior Art
For convenience' sake, a semiconductor memory structure and a memory cell selection (addressing) method will first be described with reference to, for example, 16-Mega dynamic random access memory (referred to hereinafter as DRAM) which is presently on the market.
In order to assure stability in operation, the 16-Mega DRAM is partitioned into 4 memory blocks, each of which includes 16 cell array blocks. Each of the cell array blocks includes 256 K memory cells connected in a matrix form to 256 word lines and 1 K bit lines. In result, the 16-Mega DRAM comprises 64 cell array blocks constituting the 4 memory blocks.
The 4 memory blocks are discriminated according to high-order 2 bits AYA and AYB of a 12-bit column address signal AYO-AYB. The 16 cell array blocks of each of the 4 memory blocks are discriminated according to high-order 4 bits AX8-AXB of a 12 bit row address signal AXO-AXB. The low-order 8 bits AXO-AX7 of the 12-bit row address signal AXO-AXB are used to select the 256 word lines included in each of the cell array blocks. The low-order 10 bits AYO-AY9 of the 12-bit column address signal AYO-AYB are used to select the 1K bit lines included in each of the cell array blocks. The ninth and tenth bits AY8 and AY9 of the 12-bit column address signal AYO-AYB are also used to select data read and write paths of the semiconductor memory. Namely, the ninth and tenth column address signal bits AY8 and AY9 are used to selectively connect a data input/output unit to any one of the 4 memory blocks.
In a read operation under the condition that the 16-Mega DRAM has a 16-bit data access mode and a 4K refresh rate, 16-bit data are selected according to the 12 row address signal bits AXO AXB and the 10 column address signal bits AYO-AY9. The selected 16-bit data are transferred to the input/output unit through a data path selected by the ninth and tenth column address signal bits AY8 and AY9. The input/output unit outputs the inputted 16-bit data to an external circuit. In the read operation under the condition that the 16-Mega DRAM has the 16-bit data access mode and a 1K refresh rate, 16-bit data are selected according to the 10 row address signal bits AXO-AX9 and the 10 column address signal bits AYO-AY9. The selected 16-bit data are transferred to the input/output unit through the data path selected by the ninth and tenth column address signal bits AY8 and AY9. The input/output unit outputs the inputted 16-bit data to the external circuit. Here, a data access characteristic of the semiconductor memory is the number of data which can read and written from/into the semiconductor memory at a time.
The high-order 2 bits AXA and AXB of the 12-bit row address signal AXO-AXB are selectively used according to the refresh rate of the semiconductor memory as mentioned above. The high-order 2 row address signal bits AXA and AXB are under a don't care condition if they are not used to select the cell array blocks.
Generally, a column redundancy device is used in the semiconductor memory to repair a failed one of the memory cells in the cell array blocks. The column redundancy device is adapted to drive a redundancy bit line to which a redundancy memory cell is connected, instead of the normal bit line to which the failure memory cell is connected. To this end, the column redundancy device checks a logic value of an address signal from an address source to determine whether the failure memory cell is addressed by the address signal. If it is determined that the failure memory cell is addressed by the address signal, the column redundancy device enables the redundancy bit line to which the redundancy memory cell is connected, while disabling the normal bit line to which the failure memory cell is connected. To determine whether the failure memory cell is addressed by the address signal, the column redundancy device comprises fuses which may be cut by a manufacturer and MOS transistors which are driven in response to an address decoding signal.
However, in such a conventional column redundancy device for the semiconductor memory, when a few high-order bits of the address signal are not used with an increase in the refresh rate, the fuses connected to the unused address signal bits are unconditionally cut. For this reason, in the case where a few high-order bits of the address signal are not used, the redundancy memory cells are unnecessarily consumed, resulting in a reduction in a repairing efficiency of the failure memory cells. The problem with the above-mentioned conventional column redundancy device for the semiconductor memory will hereinafter be described in detail with reference to FIG. 1.
Referring to FIG. 1, there is shown a circuit diagram of the conventional column redundancy device for the semiconductor memory. As shown in this drawing, the conventional column redundancy device comprises a precharge PMOS transistor MP1 connected between a supply voltage source Vcc and a node 11, and a row fuse box 10 connected to the node 11. The precharge PMOS transistor MP1 has a gate for inputting a precharge control signal PRE. When the precharge control signal PRE is low in logic, the precharge PMOS transistor MP1 is turned on to transfer a supply voltage from the supply voltage source Vcc to the node 11. As a result, the supply voltage from the supply voltage source Vcc is maintained on the node 11.
The row fuse box 10 is driven in response to row address combination signals RA89, RA/89, RA8/9, RA/8/9, RAAB, RA/AB, RAA/B and RA/A/B with different logic values to determine whether any one of the 16 cell array blocks to be repaired is addressed in each of the 4 memory blocks. To this end, the row fuse box 10 includes eight fuzes Fr1-Fr8 connected in parallel between the node 11 and a ground voltage source Vss, and eight NMOS transistors Mr1-Mr8, each of which is connected between a corresponding one of the fuzes Fr1-Fr8 and the ground voltage source Vss.
The eight fuzes Fr1-Fr8 may be selectively cut and programmed by the manufacturer. As being programmed, seven of the eight fuzes Fr1-Fr8 may be cut except only one.
The eight NMOS transistors Mr1-Mr8 have gates for inputting the row address combination signals RA89, RA/89, RA8/9, RA/8/9, RAAB, RA/AB, RAA/B and RA/A/B, respectively. The NMOS transistors connected to the cut fuses have no effect on the voltage on the node 11. On the other hand, the NMOS transistor Mri connected to the uncut fuse is selectively driven in response to the logic state of the corresponding row address combination signal to bypass the voltage on the node 11 to the ground voltage source Vss.
For example, assume that seven Fr2-Fr8 of the eight fuzes Fr1-Fr8 are cut and only the remaining one fuse Fr1 is operable. In this case, the NMOS transistor Mr1 is turned on when the row address combination signal RA89 is high in logic. As being turned on, the NMOS transistor Mr1 bypasses the voltage precharged on the node 11 to the ground voltage source Vss. At this time, a low logic signal with a ground voltage from the ground voltage source Vss is generated on the node 11. The low logic signal on the node 11 indicates that a cell array block corresponding to the row address combination signal RA89 is not selected (addressed).
On the contrary, in the case where the row address combination signal RA89 is low in logic, the NMOS transistor Mr1 is turned off to block a current path between the fuse Fr1 and the ground voltage source Vss. As a result, a high logic signal with the precharged voltage is generated on the node 11. The high logic signal on the node 11 indicates that the cell array block corresponding to the row address combination signal RA89 is selected (addressed).
The conventional column redundancy device further comprises a first inverter GI1 for buffering and inverting a column path start signal /CS, and a NAND gate GN1 for inputting the first logic signal from the node 11. When the column path start signal inverted by the first inverter GI1 is high in logic, the NAND gate GN1 inverts the first logic signal from the node 11 and generates the resultant second logic signal. On the contrary, when the column path start signal inverted by the first inverter GI1 is low in logic, the NAND gate GN1 generates the second logic signal which is high in logic regardless of a logic state of the first logic signal from the node 11. The second logic signal from the NAND gate GN1 is inverted by a second inverter GI2 and then applied to an output line 13.
The conventional column redundancy device further comprises a column fuse box 12 connected between the output line 13 and the ground voltage source Vss. The column fuse box 12 is driven in response to the column address signal bits AY0, /AY0, AY1, /AY1, . . . , AY7 and /AY7 with different logic values to determine whether a bit line connected to a memory cell to be repaired is selected (addressed). To this end, the column fuse box 12 includes sixteen fuses Fc1-Fc16 connected in parallel between the output line 13 and the ground voltage source Vss, and sixteen NMOS transistors Mc1-Mc16, each of which is connected between a corresponding one of the fuses Fc1-Fc16 and the ground voltage source Vss.
The sixteen fuses Fc1-Fc16 may be selectively cut and programmed by the manufacturer to detect a column address of the failure memory cell. As being programmed, fifteen of the sixteen fuses Fc1-Fc16 may be cut except only one.
The sixteen NMOS transistors Mc1-Mc16 have gates for inputting the column address signal bits AY0, /AY0, AY1, /AY1, . . . , AY7 and /AY7, respectively. The NMOS transistors connected to the cut fuses have no effect on a voltage on the output line 13. On the other hand, the NMOS transistor connected to the uncut fuse is selectively driven in response to the logic state of the corresponding column address signal bit to bypass the voltage on the output line 13 to the ground voltage source Vss.
In the case where the column address signal has a logic value programmed by the manufacturer, the column fuse box 12 maintains the voltage on the output line 13 as it is. Thus generated on the output line 13 is a column redundancy control signal RDY which is high in logic. On the contrary, in the case where the column address signal has a logic value different from that programmed by the manufacturer, the column fuse box 12 bypasses the voltage on the output line 13 to the ground voltage source Vss. As a result, the column redundancy control signal RDY generated on the output line 13 goes low in logic. When being high in logic, the column redundancy control signal RDY from the output line 13 drives a redundancy bit line connected to a redundancy memory cell (not shown).
The row address combination signals RA89, RA/89, RA8/9, RA/8/9, RAAB, RA/AB, RAA/B and RA/A/B are produced by selectively combining the high-order 4 bits AX8-AXB of the 12-bit row address signal AX0-AXB. In this connection, the row fuse box 10 is driven in response to the high-order 4 bits AX8-AXB of the 12-bit row address signal AX0-AXB to determine whether any one of the 16 cell array blocks is selected in each of the 4 memory blocks.
However, when the refresh speed is enhanced from 4K cycle to 1K cycle, the high-order one or more bits of the 12-bit row address signal AX0-AXB are under the don't care condition so that they are not used to select the cell array blocks. For this reason, the fuses connected to the unused row address signal bits must be unconditionally cut. Also, the addressing is simultaneously performed with respect to the cell array blocks corresponding to the number of logic values deducible from the unused row address signal bits. As a result, three redundancy memory cells are unnecessarily consumed in repairing one failure memory cell. The unnecessary consumption of the redundancy memory cells results in the reduction in the repairing efficiency of the failure memory cells with the increase in the refresh speed of the semiconductor memory.